This invention relates to a switching system for switching information such as voice information and data to transmit by time-division multiplexing by use of fixed-length cells, each having a header for routing, and particularly to a switching system suitable for switching, in an integrated manner, information essentially suitable for line switching, such as voice information together with information such as data which occurs as a burst.
There has been a requirement for a flexible and economical switching system capable of handling, in an integrated manner, communication of various nature (including burst and real-time communication) at diverse bit rates ranging from a typical bit rate of voice on the phone (64 Kb/s), low-speed data transmission (several 100 b/s) and video signals (several Mb/s).
A promising scheme to meet this requirement is a method of switching all information uniformly by using fixed-length cells, each having a header including information for routing. One example of this is a switching system which has been proposed by the present applicant in a paper entitled "A Study on an Integrated Switching Network" for National Convention in commemoration of the 70th anniversary of the foundation of the Institute of electronics, Information and Communication Engineers of Japan, 1987, Switching Division (hereafter referred to as the literature (1)).
In the above switching system, all information is transferred by using fixed-length blocks called cells. The switching system is arranged such that the space-division switch of the header drive type is used as a basic element in switching information, and a time switch function is provided for each incoming highway to avoid a collision in the space-division switch among a plurality of cells having the same destination. Furthermore, a memory for switching operation and a buffer memory for queuing are provided in the time switch function to permit two modes--the line switching mode which requires real time transmission like and the burst switching mode for transmitting data which occurs in burst, in which data transmission delay is allowed to some extent. In processing, the cells for line switching mode are not passed through the buffer memory and these cells are given priority for real time processing, while the cells for burst switching mode are placed in a queue in the buffer memory and processed when there is a free space in time slot.
Another example is a "TDM Switching System" disclosed in JP-A-59-135994. This publication does not clearly suggest the concept of handling two modes of communication, the line switching mode and the burst switching mode, but this switching system is provided with a function to replace the fixed-length cells according to the time base by use of the buffer memory. When the cells are replaced, the same buffer memory is used for queuing and switching of the cells. In order to achieve queuing, a queue unit is provided in which the addresses of the buffer memory to write the cells at are stored classified by the destinations of the cells.
In switching operations by use of the fixed-length cells, since the destinations of the cells are not distributed evenly, it can happen that the cells bound for the same destination are concentrated and congested for a while or the cells are lost by overflow of the memory. In the literature (1) by the present applicant mentioned earlier, a buffer memory is provided for the outgoing highway for each destination to avoid the congestion of the cells. Each of the buffer memories need to have capacity for storing all cells that do not overflow the memory capacity. A buffer memory needs to be provided for each destination. This arrangement has a problem of requiring a large number of memory devices.
On the other hand, in the switching system mentioned in the second place (JP-A-59-135994), only one buffer memory is provided for all inputs, and a plurality of queuing means which store only the addresses of the buffer memory are provided for the respective destinations. In this arrangement, the clustering of the cells for certain destinations can be handled by the relatively small memory capacity. However, the write addresses in the buffer memory are used periodically, so that logically, this arrangement is equivalent to having a buffer memory divided fixedly into the memory regions corresponding to the respective destinations. And, when the cells in a queue exceed a certain number, even if there remain cells yet to be read out, it happens that data in the buffer memory is overwritten. If this occurs, the cells on which new cells are written are lost. This is another problem.
In order to solve the above problems, the present applicant proposes in U.S. Pat. No. 4,910,731 corresponding to JP-A-63-102512 that in a switching system for switching operation by multiplexing incoming highways in time division, writing the cells that have arrived into the buffer memory, reading the cells in a proper sequence, demultiplexing and distributing the cells into a plurality of outgoing highways, the switching system comprises an FIFO (First In First Out) buffer for storing empty addresses of the buffer memory (called the empty address FIFO), and means for controlling the addresses currently used for the respective outgoing highways, and a so-called empty address chain whereby in writing a cell into the buffer memory, an empty address is taken from the data output of the above-mentioned empty address FIFO, and in reading a cell from the buffer memory, the address at which the cell has been read is returned to the input of the above-mentioned empty address FIFO.
According to the switching system arranged as described, as cells arrive and are written into the buffer memory, empty addresses are obtained from the one empty address FIFO regardless of the destinations or outgoing highways of the cells, so that the cells can be written in any region of the buffer memory so long as there is an empty space in the buffer memory. Even if there is irregularity in the distribution of the destinations of the cells that arrive, that is, even if the cells are clustered for certain outgoing highways, there should be corresponding decreases in the cells bound for the destinations other than the above-mentioned destinations for which the cells are clustered. Therefore, the total capacity of the buffer memory that is required is unchanged.
Another advantage is that until a cell is read out, the address at which the cell is stored is not returned to the empty address FIFO, so that it never happens that a newly-arrived cell is overwritten on the same address and the cell that has existed there is lost.